1. Field of the Invention
The present invention relates to a low frequency detection circuit, and more particularly, to an improved low frequency detection circuit, wherein a delay locked loop circuit for a semiconductor memory being operated at a high frequency can also be operated at a low frequency.
2. Description of the Background Art
The composition of a conventional sub-delay generation circuit will now be described with reference to the accompanying drawings.
FIG. 1 shows a negative delay signal generation circuit according to the conventional art. As shown therein, the circuit includes a pulse generator 10 for receiving an externally applied clock signal CK and generating a one shot pulse signal S1, a delay array 11 for receiving the one shot pulse signal S1 and outputting a delayed one shot pulse signal S2, a forward delay array 12 for receiving the delayed one shot pulse signal S2 and outputting a plurality of delay signals DS1-DS6, a mirror control circuit 13 for receiving the plurality of delay signals DS1-DS6 and outputting a plurality of locking signals S3-S8 in accordance with the one shot pulse signal S1, a backward delay array 14 for receiving the plurality of locking signals S3-S8 and outputting sequentially delayed output signals DS7-DS12, a dummy delay array 15 for receiving the output signals DS7-DS12 of the backward delay array 14 and decreasing power of the output signals DS7-DS12, and a delay array 16 for receiving and delaying the output signal DS12 of the backward delay array 14 and outputting a negative delay signal CKO.
Here, the negative delay signal generation circuit will now be explained in further detail.
The pulse generator 10 includes an inverter 11 for inverting a clock signal CK, a NAND gate ND1 for NANDing the clock signal CK and the output signal of the inverter I1, and an inverter I2 for inverting an output signal of the NAND gate ND1 and outputting a one shot pulse signal S1.
The delay array 11 includes inverters I3, I4 and buffers B1, B2 which are serially connected and for receiving and delaying the one shot pulse signal S1.
The forward delay array 12 includes a plurality of delay arrays D1-D6 serially connected with each other and for receiving the delayed one shot pulse signal S2 and respectively outputting the delayed one shot pulse signals DS1-DS6. Here, the delay array D1 includes a NAND gate ND2 for NANDing the delayed one shot pulse signal S2 and the source voltage Vcc, and an inverter 15 for inverting the output signal of the NAND gate ND2. Also, the other delay arrays D2-D6 are provided in the same as the delay array D1 in composition.
The mirror control circuit 13 includes a plurality of NAND gates ND3-ND8 for NANDing the output signals DS1-DS6 of the forward delay circuit 12 and the one shot pulse signal Si.
The backward delay circuit 14 includes a plurality of delay arrays D7-D12 for receiving a plurality of locking signals S30S8 outputted from the mirror control circuit 13 and sequentially delaying the received values. Here, the delay array D7 includes a NAND gate ND9 for NANDing the input signal S3 and the source voltage Vcc, and an inverter 16 for inverting the output signal of the NAND gate ND9. The other delay arrays D8-D12 is also composed of the same as the delay array D7 in circuit device composition.
The dummy delay array 15 is composed of a plurality of NAND gates ND10A-ND10F for respectively NANDing the plurality of locking signals DS7-DS12 and the ground voltage Vss.
The delay array 16 includes inverters 17, 18 serially connected to each other to delay the output signal DS12 of the backward delay circuit 14.
The operation of the conventional negative delay signal generation circuit will now be explained with reference to FIGS. 2A through 2G.
The pulse generator 10 which has received a clock signal CK as shown in FIG. 2A, generates the one shot pulse signal S1 delayed by time period t1 and having pulse width PW1, as shown in FIG. 2B, and outputs the generated value to the delay array 11 and the mirror control circuit 13. The delay array 11 which has received the one shot pulse signal S1, as shown in FIG. 2C, delays the received value by time period t2 and outputs the one shot pulse signal S2 to the forward delay circuit 12. The plurality of serially connected delay arrays D1-D6 in the forward delay circuit 12 which receives the delayed one shot pulse signal S2 respectively delay the delayed one shot pulse signal S2 and accordingly output a plurality of output signals DS1-DS6. Then, the NAND gate ND13 of the mirror control circuit 13 NANDs the signal DS6 outputted from the delay array D6 after being delayed by t3 of the signal S2 as show in FIG. 2D, and the one shot pulse signal S1 after the time period t2+t3 lapses further than the previous one shot pulse signal as shown in FIG. 2B, and then outputs the locked signal S3 as shown in FIG. 2E. Then, the backward delay circuit 14 sequentially delays the output signal locked in the mirror control circuit 13, and outputs the delayed locking signal DS12 as shown in FIG. 2F.
The second delay array 16 receiving the delayed locking signal DS12, as show in FIG. 2G, delays the output signal of the mirror control circuit 13 by time period t4, and delays the delayed locking signal DS12 before the third clock signal CK of the clock signal CK is outputted and then outputs the negative delay signal CKO.
The conventional negative delay signal generation circuit as described above may utilize the negative signal generated by receiving the clock signal as a system internal clock signal when the input signal is in a high frequency. However, the conventional negative delay signal generation circuit disadvantageously fails to output a negative delay signal because the mirror control circuit 13 for receiving the output signal of the forward delay circuit and the one shot pulse signal outputted from the pulse generator causes timing skew for thereby being unable to output a locked signal to the backward delay circuit.
Therefore, an additional circuit should be provided in order to test a semiconductor chip operation in a low frequency by use of the conventional negative delay signal generation circuit, thereby incurring an increased circuit size and complication.